1. Field of the Invention
The present invention relates to an active matrix type display apparatus that is capable of gray scale display by applying pulse-like voltages having different duty ratios to pixel electrodes.
2. Description of the Related Art
FIG. 18 shows an exemplified configuration of a conventional active matrix type liquid crystal display apparatus that is capable of gray scale display by using analog voltages having different voltage levels. In FIG. 18 and the following description, it is assumed for simplification that the liquid crystal display apparatus has pixels aligned in three rows and three columns.
The liquid crystal interposed display apparatus includes a pair of substrates 11 and 12 opposing each other with liquid crystal interposed therebetween. On one surface of the substrate 11 opposing the substrate 12 are formed pixel electrodes P11 through P33 made of transparent conductive films in a matrix of three rows and three columns. In the vicinity of the pixel electrodes P11 through P33 are disposed three row electrodes (gate lines) G1 through G3 and three column electrodes (source lines) S1 through S3 so that the row electrodes G1 through G3 cross the column electrodes S1 through S3 at right angles. On the respective crossings between the row electrodes G1 through G3 and the column electrodes S1 through S3 are disposed thin film transistors (TFTs) Q11 through Q33. Each of the pixel electrodes P11 through P33 is connected to the corresponding column electrode S1, S2 or S3 via the source and the drain of one of the TFTs Q11 through Q33 corresponding to the pixel electrode. The gate terminal of each of the TFTs Q11 through Q33 is connected to the corresponding row electrode G1, G2 or G3. On the entire surface of the substrate 12 opposing the substrate 11 is formed a counter electrode. Accordingly, liquid crystal cells are formed between the counter electrode on the substrate 12 and the pixel electrodes P11 through P33 on the substrate 11 by interposing the liquid crystal therebetween. As a result, the liquid crystal display apparatus is capable of the gray scale display by varying the permeability of light depending upon the voltages charged at the respective pixel electrodes P11 through P33 (i.e., potential differences with the counter electrode).
This liquid crystal display apparatus includes, as peripheral circuits, a timing controller 13, a gray scale voltage source 15, a column electrode driving circuit 16 and a row electrode driving circuit 17. The timing controller 13 receives a display data D, a vertical synchronizing signal VS, a horizontal synchronizing signal HS and a dot clock signal CLK, all of which are externally supplied, and generates various synchronizing signals. The timing controller 13 transfers the generated synchronizing signals to the gray scale voltage source 15, the column electrode driving circuit 16 and the row electrode driving circuit 17. The column electrode driving circuit 16 is supplied with the display data D as well as the synchronizing signals.
The gray scale voltage source 15 generates a plurality of analog gray scale voltages V0 through V3 having different voltage levels depending upon the respective gray levels of the gray scale display, and supplies the analog gray scale voltages V0 through V3 to the column electrode driving circuit 16. The gray scale voltage source 15 also generates a counter electrode signal VC whose voltage level is varied in each vertical scanning term TV based on a synchronizing signal supplied by the timing controller 13, and supplies the counter electrode signal VC to the counter electrode on the substrate 12.
The row electrode driving circuit 17 generates three kinds of row electrode scanning signals OG1 through OG3 that are successively activated in each horizontal scanning term TH based on the synchronizing signals supplied by the timing controller 13, and transfers each of the row electrode scanning signals OG1 through OG3 to the corresponding row electrode G1, G2 or G3. When the row electrode scanning signals OG1 through OG3 respectively output, the row electrodes G1 through G3 are activated, and the corresponding TFTs Q11 through Q33 connected to the row electrodes G1 through G3 become conductive. Therefore, for example, when the row electrode scanning signal OG2 output to the row electrode G2 is activated, all the TFTs Q21, Q22 and Q23 connected to the row electrode G2 become conductive, thereby connecting the corresponding row of pixel electrodes P21, P22 and P23 to the respective column electrodes S1 through S3.
The column electrode driving circuit 16 serial/parallel converts the display data D, that is, a digital signal, for three pixels at one time, selects one of the analog gray scale voltages V0 through V3 supplied by the gray scale voltage source 15 so as to correspond to each display data D for the three pixels, and outputs the selected voltage as column electrode driving signals OS1 through OS3 to the respective column electrodes S1 through S3 on the substrate 11 simultaneously.
FIG. 19 shows a specific exemplified configuration of the column electrode driving circuit 16. This drawing shows merely part of the circuit where a column electrode driving signal OSi is output to one column electrode Si (wherein i is 1, 2 or 3). This means that the number of such a circuit as is shown in FIG. 19 in the actual column electrode driving circuit 16 is equal to the number of the column electrodes Si. Further, it is assumed in the following description that the display data D is composed of two data bits d0 and d1 or a gray scale display with four levels.
The display data D for three pixels are successively transferred in serial from the timing controller 13 to the column electrode driving circuit 16 in one horizontal scanning term TH, whereas the two data bits d0 and d1 in the display data D for one pixel are transferred to the column electrode driving circuit 16 in parallel. The data bits d0 and d1 are latched in a sample latch circuit 16a in response to a sampling pulse TSi. The sampling pulse TSi is one of the synchronizing signals supplied by the timing controller 13, and in the display apparatus of FIG. 18, three sampling pulses TS1 through TS3 are transferred by the timing controller 13. The sampling pulses TS1 through TS3 successively rise every time the display data D for one pixel is supplied. This is repeated in each horizontal scanning term TH in which the display data D for three pixels are supplied. The data bits d0 and d1 latched in the sample latch circuit 16a are latched in a hold latch circuit 16b in response to a hold pulse OE. The hold pulse OE is also one of the synchronizing signals supplied by the timing controller 13 and rises once in each horizontal scanning term TH. Therefore, the data bits d0 and d1 for three pixels transferred in one horizontal scanning term TH are successively latched in the sample latch circuit 16a and simultaneously latched in the hold latch circuit 16b so as to be serial/parallel converted.
The data bits d0 and d1 latched in the hold latch circuit 16b are transferred to a decoder circuit 16c. The decoder circuit 16c activates one of four outputs S0 through S3 in accordance with the digital values of the data bits d0 and d1 received as inputs D0 and D1. The four outputs S0 through S3 are transferred to the control input terminals of four analog switches ASW0 through ASW3, respectively. The analog switches ASW0 through ASW3 select one of the analog gray scale voltages V0 through V3 supplied by the gray scale voltage source 15 in accordance with the outputs S0 through S3 of the decoder circuit 16c, and output the selected voltage as the column electrode driving signal OSi. The column electrode driving signal OSi is supplied to the corresponding column electrode Si.
The operation of such a liquid crystal display apparatus will now be described based on a timing diagram shown in FIG. 20.
Since the pixel electrodes P11 through P33 are aligned in the matrix with the three rows and the three columns, one period of the vertical synchronizing signal VS includes three periods of the horizontal synchronizing signal HS. One period of the horizontal synchronizing signal VS corresponds to a vertical scanning term TV and one period of the horizontal synchronizing signal HS corresponds to a horizontal scanning term TH. The display data D for three pixels are transferred in each horizontal scanning term TH, and the display data D for all the pixel electrodes P11 through P33 (which are denoted by reference numerals D11 through D33 in FIG. 20 for the convenience of the description) are transferred in one horizontal scanning term TV.
The column electrode driving signals OS1 through OS3 output to the column electrodes S1 through S3 correspond to the analog gray scale voltages V0 through V3 corresponding to the respective display data D11 through D33. For example, the column electrode driving signal OS2 is one of the analog gray scale voltages V0 through V3 corresponding to the display data D12, D22 and D32, and is switched in each horizontal scanning term TH. Further, the column electrode driving signal OS2 is one of he analog gray scale voltages V0 through V3 corresponding to, for example, the display data D12 in a horizontal scanning term TH subsequent to a horizontal scanning term TH when the display data D12 is transferred to the column electrode driving circuit 16.
Any one of the row electrode scanning signals OG1 through OG3 output to the row electrodes G1 through G3 successively undergoes a low to high transition in each horizontal scanning term TH. Specifically, the first row electrode scanning signal OG1 is at a high level in a second horizontal scanning term TH in one vertical scanning term TV, the second row electrode scanning signal OG2 is at a high level in a third horizontal scanning term TH in the same vertical scanning term TV, and the third row electrode scanning signal OG3 is at a high level in a first horizontal scanning term TH in the subsequent horizontal scanning term TV. Such level changes are repeated in each vertical scanning term TV, whereas the row electrode scanning signals OG1 through OG3 are actually at a high level not in the entire horizontal scanning term TH but in a row electrode scanning term TG that accounts for a great part of the horizontal scanning term TH.
The analog gray scale voltages V0 through V3 are driving signal having different fixed voltage levels. The voltage levels of the analog gray scale voltages V0 through V3 can be switched in each vertical scanning term TV so as to be inverted at the height. Also, the counter electrode signal VC supplied to the counter electrode on the substrate 12 is a driving signal having a desired voltage level, and can be switched between higher and lower potentials in each vertical scanning term TV. The absolute value of a potential difference between the counter electrode signal VC and each of the analog gray scale voltages V0 through V3 is constant, respectively, and merely the polarity of the potential difference is inverted in each vertical scanning term TV. Accordingly, a voltage whose polarity is inverted in each vertical scanning term TV is applied between each of the pixel electrodes P11 through P33 on the substrate 11 and the counter electrode on the substrate 12. Such AC drive prevents the liquid crystal from degrading. As alternative AC drive, the counter electrode signal VC is always kept at a fixed voltage level, and the voltage levels of the analog gray scale voltages V0 through V3 alone are switched to be symmetrical about the fixed voltage level.
Now, the case where the display data D22 corresponds to the analog gray scale voltage V2 will be exemplified. Since a potential difference between the analog gray scale voltage V2 and the counter electrode signal VC is applied between the pixel electrode P22 and the counter electrode in a row electrode scanning term TG when the row electrode scanning signal OG2 is at a high level, the voltage waveform at the pixel electrode P22 is obtained, by using the potential of the counter electrode as a reference, as is shown as a waveform VP22 in FIG. 20. Specifically, in the row electrode scanning term TG when the row electrode scanning signal OG2 is at a high level, the TFT Q22 is conductive so that the pixel electrode P22 charged/discharged to have a voltage level defined by the analog gray scale voltage V2. Then, this voltage level is maintained until the row electrode scanning signal OG2 is activated again by cutting off the TFT Q22. When the row electrode scanning signal OG2 is activated again, the pixel electrode P22 is charged/discharged to have a reverse voltage level with the same absolute value. This procedure is repeated thereafter.
In this conventional liquid crystal display apparatus, the four kinds of analog gray scale voltages V0 through V3 are generated in the gray scale voltage source 15, and the number of the kinds of the voltages is equal to the number of the levels of the gray scale display. These analog gray scale voltages V0 through V3 are, however, generated in an analog circuit generally including a combination of an operational amplifier, a transistor for current amplification and the like. Therefore, such an analog circuit occupies large part in the entire driving circuit not only in the mounting space but also in the production cost. In addition, when the number of the levels of the gray scale display is increased, a larger number of kinds of analog gray scale voltages are required, resulting in making this problem more serious. Moreover, the number of the analog switches ASW0 through ASW3 as shown in FIG. 19 required for each of the column electrodes S1 through S3 in the column electrode driving circuit 16 is identical to the number of the levels of the gray scale display, i.e., four in the aforementioned description. Such a large number of analog switches also occupy a large space in each chip. Further, the number of the analog switches ASW is accumulatively increased when the number of the levels of the gray scale display is increased or when the number of the column electrodes is increased to attain high resolution.
In order to solve the above-mentioned problems, an active matrix type liquid crystal display apparatus for the gray scale display has been conventionally developed in which pulse-like voltages having different duty ratios are applied to pixel electrodes.
An equivalent circuit for one pixel in such an active matrix type liquid crystal display apparatus is shown in FIG. 21. As is shown in FIG. 21, a pixel capacitance CP, which is formed by a pixel electrode P and a counter electrode together with liquid crystal sandwiched therebetween, is connected to a column electrode S via the source and the drain of a TFT Q whose gate is connected to a row electrode G. A circuit diagram as is shown in FIG. 22 can be obtained when the ON resistance of the TFT Q is indicated by RON, and the capacitance of the column electrode S and the distributed capacitance between the column electrode S and the counter electrode are respectively indicated by a column electrode resistance RS and a column electrode capacitance CS, which are concentrated constants thereof. Now, a circuit composed of the ON resistance RON and the pixel capacitance CP and a circuit composed of the column electrode resistance RS and the column electrode capacitance CS will be studied. When a voltage V is applied in a stepwise manner to such a series circuit composed of a resistance R and a capacitance C, the terminal voltage v of the capacitance C is varied with time t as represented by the following equation 1: ##EQU1## The time constant in this case is a product RC of the resistance R and the capacitance C. Further, when the terminal voltage V of the capacitance C is regarded as the output of this circuit, this circuit can be considered to have a low-pass filter characteristic in accordance with the time constant RC, and hence, the circuit has a function to smooth and average an input voltage. Accordingly, when a pulse signal in which two kinds of voltages VSH and VSL are alternately repeated as is shown in FIG. 23 is applied to this circuit, the capacitance C is charged with an average voltage obtained by averaging the voltages VSH and VSL on the basis of a duty ratio m:n of the pulse signal as represented by equation 2, if the time constant RC is sufficiently long as compared with a period T of the pulse signal: ##EQU2## This means that, as is shown in FIG. 24, the terminal voltage V shown with a heavy line is gradually averaged through the repeat of charge/discharge. When the value of m of the duty ratio m:n of the pulse signal is large, the terminal voltage v is averaged to be at a high voltage level, and when the value of m is small, it is averaged to be at a low voltage level. When the voltage to be charged in the pixel capacitance CP is varied by applying such pulse signals having different duty ratios to the column electrode S, the gray scale display can be realized without using an analog gray scale voltage by merely supplying the two kinds of voltages VSH and VSL.
In an actually used liquid crystal display apparatus, although the ON resistance RON is generally larger than the column electrode resistance RS and the pixel capacitance CP is generally smaller than the column electrode capacitance CS, the time constant RON.times.CP of the ON resistance RON and the pixel capacitance CP is sufficiently longer than the time constant RS.times.CS of the column resistance RS and the column electrode capacitance CS. Therefore, the charging/discharging characteristic in the case where the pixel capacitance CP is charged/discharged is defined not by the time constant RS.times.CS of the column electrode S but by the time constant RON.times.CP in each pixel.
An exemplified configuration of the conventional liquid crystal display apparatus using the application of such a pulse-like voltage is shown in FIG. 25. This liquid crystal display apparatus has substantially the same configuration as that shown in FIG. 18, and hence, the same reference numerals are used to refer to elements having the same function and the description thereof is omitted.
This liquid crystal display apparatus includes a gray scale signal generating circuit 14 for generating four kinds of gray scale pulse signals GS0 through GS3 based on a synchronizing signal transferred by the timing controller 13. The gray scale pulse signals GS0 through GS3 are supplied to the column electrode driving circuit 16. The gray scale voltage source 15 supplies, instead of the analog gray scale voltages V0 through V3, the two kinds of voltages VSH and VSL to the column electrode driving circuit 16.
The gray scale signal generating circuit 14 includes, as is shown in FIG. 26, four pulse signal generating circuits 1 and four EXNOR circuits 3. The four pulse signal generating circuits 1 generate four kinds of pulse signals SP0 through SP3 having the same period but different duty ratios based on a clock signal CK and a reset signal RES transferred by the timing controller 13. The pulse signals SP0 through SP3 are transferred to one input terminal of the corresponding EXNOR circuit 3. The other input terminal of the EXNOR circuit 3 is supplied with an AC driving signal AD that is transferred by the timing controller 13 and is inverted in each vertical scanning term TV. The EXNOR circuit 3 calculates an exclusive OR of each of the pulse signals SP0 through SP3 and the AC driving signal AD, and outputs one of the gray scale pulse signals GS0 through GS3 that have different duty ratios and are inverted (i.e., made into an inverse) in each vertical scanning term TV, as is shown in FIG. 28 described in detail below.
A specific exemplified configuration of the column electrode driving circuit 16 supplied with the gray scale pulse signals GS0 through GS3 is shown in FIG. 27. Similarly to FIG. 19, this drawing also shows merely part of the circuit where a column electrode driving signal OSi is output to one column electrode Si, and it is also assumed that display data D is composed of two data bits d0 and d1.
The Sample latch circuit 16a, the hold latch circuit 16b and the decoder circuit 16c have the same functions as those used in the column electrode driving circuit 6 of FIG. 19, and hence, the description thereof is omitted. The four outputs of the decoder circuit 16c are transferred to one input terminal of each of four AND circuits 16d. Each AND circuit 16d selects one of the four gray scale pulse signals GS0 through GS3 in accordance with the outputs S0 through S3 of the decoder circuit 16c and outputs the selected signal. The outputs of the respective AND circuits 16d are put together at a four-input NOR circuit 16e to be transferred to the input terminal of a buffer circuit 16f. The buffer circuit 16f converts one of the gray scale pulse signals GS0 through GS3 at a logical level transferred through the four-input NOR circuit 16e into a column electrode driving signal OSi that is applicable to drive the column electrodes S1 through S3, and outputs the converted signal. Therefore, in the column electrode driving signal OSi, the voltages VSH and VSL supplied by the gray scale voltage source 15 are alternately repeated at the same duty ratio as that of the selected gray scale pulse signal GS0, GS1, GS2 or GS3. The column electrode driving signal OSi is output to the corresponding column electrode Si.
The operation of this liquid crystal display apparatus will now be described based on a timing diagram shown in FIG. 28. With regard to the vertical synchronizing signal VS, the horizontal synchronizing signal HS, the display data D, the column electrode driving signals OS1 through SO3 and the row electrode scanning signals OG1 through OG3, the above description referring to FIG. 20 is applicable, and hence the description is omitted.
The gray scale pulse signals GS0 through GS3 are pulse signals having the same period but different duty ratios, and are also switched to have inverted duty ratios in each vertical scanning term TV for the AC drive. Also the counter electrode signal VC corresponding to these pulse signals is switched to have two kinds of voltages approximate to the voltages VSH and VSL in each vertical scanning term TV.
The case where the display data D22 has a value corresponding to the gray scale pulse signal GS2 will be herein exemplified. In a row electrode scanning term TG when the row electrode scanning signal OG2 is at a high level, a potential difference between the counter electrode signal VC and the column electrode driving signal OS2, in which the voltages VSH and VSL are alternately repeated at the same duty ratio as that of the gray scale pulse signal GS2, is applied to the pixel electrode P22. Accordingly, the voltage waveform at the pixel electrode P22 is obtained, by using the potential at the counter electrode as a reference, as is shown as a waveform VP22 in FIG. 28. A charging/discharging circuit composed of the conductive TFT Q22 end the pixel electrode P22 has a charging/discharging characteristic defined by the time constant RON.times.CP, and hence, the oscillating voltage is averaged. Therefore, when the pixel electrode P22 is alternately supplied with the voltages VSH and VSL, the voltage waveform VP22, in consideration of the actual low-pass filter characteristic, is averaged in accordance with the duty ratio of the gray scale pulse signal GS2 as is shown with a heavy line in FIG. 28. The averaged voltage level is maintained until the row electrode scanning signal OG2 is activated again by cutting off the TFT Q22. When the row electrode scanning signal OG2 is activated again, the pixel electrode P22 is charged/discharged to have a voltage level having the same absolute value and reverse polarity. This procedure is repeated thereafter.
As a result, in the conventional liquid crystal display apparatus shown in FIG. 25, the gray scale voltage source 15 merely supplies the two kinds of voltages VSH and VSL regardless of the number of the levels of the gray scale display. In addition, the analog switches ASW in the column electrode driving circuit 16 of FIG. 19 are replaced with a digital circuit composed of the AND circuits 16a, the four-input NOR circuit 16e and the buffer circuit 16f as shown in FIG. 27. Therefore, the problem caused by the analog circuit for the gray scale display that it requires a high cost and a large area for mounting parts can be overcome.
The periods of the gray scale pulse signals GS0 through GS3 are set to be sufficiently short as compared with the time constant RON.times.CP of the charging/discharging circuits of the pixel electrodes P11 through P33 of FIG. 22, so that the oscillating voltages of the column electrode driving signals OS1 through OS3 can be averaged without fail. Accordingly, when such oscillating voltages are applied to the column electrodes S1 through S3, the charging/discharging currents flowing through the charging/discharging circuits of the pixel electrodes P11 through P33 are directly decreased. The oscillating voltages, however, are also applied to the charging/discharging circuits of the column electrode capacitances CS of the column electrodes S1 through S3. The time constant RS.times.CS of the charging/discharging circuits of the column electrodes S1 through S3 is much shorter than the time constant RON.times.CP of the charging/discharging circuits of the pixel electrodes P11 through P33. In the case where the time constant RC is shorter than the period T as is shown in FIG. 29, the terminal voltage v cannot be averaged but continues to oscillate, thereby allowing the charging/discharging current to continuously flow. Therefore, when the oscillating voltages of the column electrode driving signals OS1 through OS3 are applied to the column electrodes S1 through S3, the charging/discharging currents repeatedly flow through the charging/discharging circuits of the column electrodes S1 through S3 having the shorter time constant RS.times.CS.
As a result, the conventional liquid crystal display apparatus using the application of the pulse-like voltage has a problem that large power is required since the charging/discharging currents wastefully flow through the column electrode capacitances CS of the column electrodes S1 through S3.